In a vertical power MOS field effect transistor (MOSFET) described in Patent Document 1, as shown in FIG. 1 and FIG. 2 of this document, minute diodes are arranged at least in one line in a region on a cell region side of the MOSFET that is adjacent to a perimeter (including a gate pad portion) of the cell region of the MOSFET, along the perimeter. When the MOSFET is switched from an ON state to an OFF state, each of the above-mentioned diodes arranged in a line in the region between the gate pad portion and the cell region of the MOSFET absorbs holes injected, in forward bias, into an N-type semiconductor layer on the drain side from the P-well and P-base shown in FIG. 2 of Patent Document 1. Accordingly, with the structure of Patent Document 1, a parasitic transistor shown in FIG. 3 of this document is prevented from turning on when the MOSFET is switched from forward bias to reverse bias.
In the structure of Patent Document 1, as shown in FIG. 2 thereof, the P-base that is the P-well of the MOSFET is electrically connected to the source electrode through a back gate.